1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device having a timing reference control function, and a method for controlling the same, and more specifically, to a technology which improves cell operation characteristics by controlling a sensing operation of a nonvolatile ferroelectric memory device by a timing reference.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
In the conventional nonvolatile ferroelectric memory, when cell data are sensed, a sensing reference voltage is set to have a proper level.
However, as a chip operation voltage of the FeRAM becomes lower, the level of the reference voltage to sense a cell also becomes lower. When the sensing voltage level of the cell data is low, a voltage margin between the sensing voltage and the reference voltage is reduced. As a result, it is difficult to determine data. Also, a sensing margin is reduced by change of the reference voltage. Therefore, it is difficult to obtain a rapid operation speed of the FeRAM chip having a 1T1C (1transistor, 1capacitor).